Dec 12, 2009
This thesis investigates the use of an FPGA to perform hardware coprocessing in a JPEG2000 implementation. JPEG2000 is the next-generation image compression standard developed by the Joint Photographic Experts Group.It is superior to the original JPEG standard in terms of performance and functionality. The thesis aims to provide VHDL modules that can be used to accelerate an existing software implementation of JPEG2000.
Author:-Edward James Brennan
University:- The University of Queensland
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