Implementing Cascade Integer Comb filter for Software Defined Radio Applications

This is a Electronics engineering project for final year students on "Implementing Cascade Integer Comb (CIC) filter for software defined radio applications". Software defined radio (SDR) is a radio in which the properties of carrier frequency, signal bandwidth, modulation, and several other characteristics are defined by software. Cascaded Integrator comb (CIC) decimation filter is useful to reduce the data sampling rate such high bandwidth applications. In this project a full-fledged digital down conversion system will be developed in VHDL for FPGA based software defined radio applications. The CIC based architecture will be implemented in VHDL and will be tested on Xilinx FPGAs. You can also Subscribe to FINAL YEAR PROJECT'S by Email for more such projects and seminar.

The CIC filter can implement an interpolation or decimation filter (see above fig.) that uses only delay and add operations and thus is well-suited for FPGA and ASIC implementation. Furthermore, the same basic filter structure can be used to handle variable sample rate conversion.


The major blocks in design would include digital I and Q carrier generators, digital mixers, decimating/interpolating CIC filters and clock distribution circuits. The blocks such as, adder, multipliers, registers and clock & control circuitry will be used in implementing these blocks.

Recommended Project: RISC Processor using the Verilog Hardware Description Language (VHDL)

In this paper, OUI is used which is SOPC builder provides to design the hardware of CIC decimation filter component. We design the software driver files for the hardware of CIC component, generate a component and establish an SOPC system in SOPC Builder. Finally, the designed system is downloaded to the device and verified in FPGA.

Author:- Ripudaman Singh Rathore and Rajat Arora

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