Design Of Efficient Multiplier Using VHDL M.Tech Project Report - Free Final Year Project's

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Mar 22, 2011

Design Of Efficient Multiplier Using VHDL M.Tech Project Report

This is a Good VLSI Project report for Electronics & communication students on Design Of Efficient Multiplier Using VHDL and this thesis was submitted in partial fulfillment of the requirements for the degree of Master of Technology in Electronics and Communication Engineering. The report is divided into 6 chapters. The objective of a good multiplier is to provide a physically compact, good speed and low power consuming chip. To save significant power consumption of a VLSI design, it is a good direction to reduce its dynamic power that is the major part of total power dissipation. You can also Subscribe to FINAL YEAR PROJECT'S by Email for more such Projects and Seminar.

This thesis propose high speed low-power multiplier algorithms. The booth multiplier will reduce the number of partial products generated by a factor of 2. The adder will avoid the unwanted addition and thus minimize the switching power dissipation. The proposed high speed low power multiplier can attain speed improvement and power reduction in the Booth encoder when compared with the conventional array multipliers.




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