Reusable SoC Verification Environment IP - Free Final Year Project's

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Aug 28, 2009

Reusable SoC Verification Environment IP

With the increase in Design complexity, the effort spent on SoC verification is increasing exponentially. With the increase in the chip complexity and reduced design cycle time there is an extensive need for reuse. We can increase reuse of the verification environment and the test-patterns for Core based design. With the increase in reuse the verification engineer can spend more effort on quality of verification rather than spending the effort for redeveloping the environment.

Reusable SoC Verification Environment IP

Reuse of checkers, external stimuli generator, and coverage metric for the module will help to boost the full system verification environment. Reusability and portability are the main focus in setting up the SoC verification environment. Reusing module level verification components (such as checkers and monitors) on top level can ensure the module functional consistency and also reduce the effort of rechecking the module.



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