3D Integration, Temperature Effects, and Modeling is thesis for Electrical engineering and Electronics Engineering. It gives the idea about needed of architecture in order to realize the increased device density and circuit functionality that future high performance ICs demand.
You can also Subscribe to FINAL YEAR PROJECT'S by Email for more such Projects. In this thesis, the limits to scaling are noted and the feasibility of overcoming these limits using 3D integration is presented.
The challenges and considerations, most notably dangerously high chip temperatures, are provided. To address the temperature concern, a mixed-mode simulator that calculates temperature as a function of position on chip is detailed.
Author:-Parker, Latise
Source:- The University of Maryland
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