Simulation of Double Gate Tunnel Field Effect Transistor (FET)

This is final year electronics project report on "Simulation of double gate tunnel field effect transistor (FET)". Tunnel FETs, which are gated p-i-n diodes whose on-current arises from band-to-band tunneling, are attractive new devices for low-power applications due to their low off-current and their potential for a small sub threshold swing. Numerical simulations of DG Tunnel FETs such as the ones presented in this thesis allow the investigation of the device physics, with the possibility to see inside a device through cross sections in 2D to obtain optimal DGTFET structure for low power application. You can also Subscribe to FINAL YEAR PROJECT'S by Email for more such projects and seminar.



Above image shows the Contour plot of Electric Field across DGTFET before optimization. The numerical simulations presented in this thesis have been carried out using a non-local band-to-band tunneling model in Silvaco Atlas. Numerical simulations based on correct underlying models are important for emerging devices, since they can provide insights about optimization before fabrication is carried out, can aid the understanding of device physics through 1D and 2D cross sections, and can be the basis for the formation of an accurate compact model.

The biggest future challenge is to successfully design and fabricate fully-optimized Tunnel FETs of both n-type and p-type, that show low off-currents beyond what is possible for conventional MOSFETs, high on-currents, and average sub-threshold swings of less than 60 mV/decade at room temperature. Use this report only for your reference and study work.

Author:- Rasika Gupta, Beena Kothari, Jyotsana Rawat, Parvati Bhandari

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